1. Field of the Invention
The present invention relates to decoder architectures. More particularly, the present invention relates to a recursive decoder architecture which performs the decoding in a parallel structure.
2. The Prior Art
In high speed data transmission over such mediums as satellite, telephone, co-axial cable, and optical fiber, very efficient and fast decoders are of critical importance. As such, in the prior art, many methods are known for decoding a binary block codeword of a specified length and having a particular dimension K, wherein 2k defines the number of possible combinations of different codewords for the specified length N. These methods typically involve decomposing the binary block codewords into several sections of parallel sub-trellises, as is understood by those of ordinary skill in the art. Decoding of the various sections of sub-trellises are then performed.
One of the most widely employed methods for decomposing the codeword into sub-trellises for decoding employs the Viterbi algorithm. In the decomposition of the binary codewords, according to the Viterbi algorithm, the decoder constructed in accordance thereby uses information from previous parallel sub-trellis sections to determine survivors for subsequent parallel sub-trellis sections. Accordingly, the parallel sub-trellises of the decoder are decoded in a sequential manner.
It is, therefore, an object of the present invention, to avoid the disadvantages presented by the sequential decoding found in Viterbi decoders, by forming a decoder wherein all of the decoding can be formed at once in parallel.
In the present invention, a recursive decoder implements a decoding method wherein a binary block codeword can be decomposed such that short decoding at a first stage can be performed in a massively parallel fashion. In subsequent stages, a series of comparisons and additions are then be made until the codeword is fully decoded.